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| Integrated Circuit Systems, Inc. AV9110 Serially Programmable Frequency Generator General Description The AV9110 generates user specified clock frequencies using an externally generated input reference, such as 14.318 MHz or 10.00 MHz crystal connected between pins 1 and 14. Alternately, a TTL input reference clock signal can be used. The output frequency is determined by a 24-bit digital word entered through the serial port. The serial port enables the user to change the output frequency on-the-fly. The clock outputs utilize CMOS level output buffers that operate up to 130 MHz. Features * * * * * * * * * Complete user programmability of output frequency through serial input data port On-chip Phase-Locked Loop for clock generation Generates accurate frequencies up to 130 MHz Tristate CMOS outputs 5 volt power supply Low power CMOS technology 14-pin DIP or 150-mil SOIC Very low jitter Wide operating range VCO Applications Graphics: The AV9110 generates low jitter, high speed pixel (or dot) clocks. It can be used to replace multiple expensive high speed crystal oscillators. The flexibility of this device allows it to generate nonstandard graphics clocks, allowing the user to program frequencies on-the-fly. Block Diagram 9110 Rev F 5/30/00 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. AV9110 Pin Configuration Clock Reference Implementations: AV9110-01 vs. AV9110-02 The AV9110 requires a stable reference clock (5 to 32 MHz) to generate a stable, low jitter output clock. The AV9 11 0 -01 is optimized to use an external quartz crystal as a frequency reference, without the need of additional external components. The AV9110-02 is optimized to accept an TTL clock reference. Either device can be used with an external crystal or accept a TTL clock reference, although extra components may be required. The various combinations implied are summarized in Figure 2 (see page 7). 14 Pin Dip, SOIC Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P I N NA M E X1 AV D D AGND VDD GND DATA SCLK CE# CLK/X GND VDD CLK OE X2 PIN TYPE Input P ow e r P ow e r P ow e r P ow e r Input Input Input Output P ow e r Power Output Input Output DESCRIPTION Crystal input or TTL reference clock. ANALOG power supply. Connect to +5V. ANALOG GROUND. Digital power supply. Connect to +5V. Digital GROUND. Serial DATA pin. SERIAL CLOCK. Clocks shift register. CHIP ENABLE. Active low, controls data transfer. CMOS CLOCK divided by X output. Digital GROUND. Digital power supply. Connect to +5V. CMOS CLOCK output. OUTPUT ENABLE. Tristates both outputs when low. Crystal input or TTL reference clock. 2 AV9110 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Voltage on I/O pins referenced to GND . . . . . . GND -0.5 V to VDD +0.5 V Operating Temperature under bias . . . . . . . . . . 0C to +70C Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics VDD = +5V10%, TA = 0 - 70 C unless otherwise stated DC/STATIC PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage 1 1 1 SYMBOL VIL VIH IIL IIH VOL VOH IOH = 8Ma ICLKr ICLKf IDD fo tr tf dt TEST CONDITIONS VDD = 5V VDD = 5V VIN = OV VIN = VDD IOL = 8Ma MIN 2.0 2.4 - TYP 25 MAX 0.8 -5 5 0.4 20 20 - UNITS V V A A V V ns ns mA Output High Voltage Input Clock Rise Time Input Clock Fall Time Supply Current 1 No load AC/DYNAMIC - Output frequency range Rise time, 20-80% Fall time, 80-20% 1 1 0.78 25pF load 25pF load 25pF load 40 - 40 125 14.318 14.318 400 130 3 3 60 32 32 32 - MHz ns ns % ps ps MHz MHz MHz ps 1 Duty cycle @ 50% Jitter, 1 sigma 1 1 1 1 Jitter, absolute Input reference freq.; AV9110-01 fREF fREF fDATA tskew Crystal input TTL input 5 0.6 - Input reference freq.; AV9110-02 Input DATA or SCLK frequency Skew, Output to Output/X1 1 Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 AV9110 Serial Programming The AV9110 is programmed to generate clock frequencies by entering data through the shift register. Figure 1 displays the proper timing sequence. On the negative going edge of CE#, the shift register is enabled and the data at the DATA pin is loaded into the shift register on the rising edge of the SCLK. Bit D0 is loaded first, followed by D1, D2, etc. This data consists of the 24 bits shown in the Shift Register Bit Assignment in Table 1, and therefore takes 24 clock cycles to load. An internal counter then disables the input and transfers the data to internal latches on the rising edge of the 24th cycle of the SCLK. Any data entered after the 24th cycle is ignored until CE# must remain low for a minimum of 24 SLCK clock cycles. If CE# is taken high before 24 clock cycles have elapsed, the data is ignored (no frequency change occurs) and the counter is reset. Tables 1 and 2 display the bit location for generating the output clock frequency and the output divider circuitry, respectively. BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ASSIGNMENT VCO frequency divider (LSB) VCO frequency divider VCO frequency divider VCO frequency divider VCO frequency divider VCO frequency divider VCO frequency divider (MSB) Reference frequency divider (LSB) Reference frequency divider Reference frequency divider Reference frequency divider Reference frequency divider Reference frequency divider Reference frequency divider (MSB) VCO pre-scale divide (0=divide by 1, 1=divide by 8 CLK/X output divide COD0 (see Table 2) CLK/X output divide COD1 (see Table 2) VCO output divide VOD0 (see Table 3) VCO output divide VOD1 (see Table 3) Outplut enable CLK (0=tristate) Output enable CLK/X (0=tristate) Reserved. Should be programmmed high (1) Reference clock select on CLK (1 = reference frequency) Reserved. Should be programmed high (1) EQUATION VARIABLE DEFAULT -01 1 1 1 1 1 1 1 0 1 0 0 1 0 0 -02 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 1 1 1 1 0 1 BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 N Integer M Integer V X R 0 0 1 0 1 1 1 1 0 1 4 AV9110 Output Divider Turth Tables Table 2 COD1 0 0 1 1 COD0 0 1 0 1 CLK/X Output Divide (X) 1 2 4 8 COD1 0 0 1 1 Table 3 COD0 0 1 0 1 VCO Output Divide (R) 1 2 4 8 Programming the PLL The AV9110 has a wide operating range but it is recommended that it is operated within the following limits: 2 MHz < fREF < 32 MHz 200 kHz < fREF = Input reference frequency M = Reference divide, 3 to 127 fVCO = VCO output frequency fCLK = CLK or CLK/X output frequency fREF < 5MHz M 50 MHz < fVCO <250 MHz fVCO < 250 MHz The AV9110 is a classical PLL circuit and the VCO output frequency is given by: fVCO = N*V* fREF M Where N = VCO divided, 3 to 127 M =m Reference divide, 3 to 127 V = Perscale, 1 or 8 The 2 output drivers then give the following frequencies: fCLK = fVCO R fCLK/X = fVCO R*X = N*V* fREF MR = fVCLK X or fREF (output mixable by bit 17) Where R, X = output dividers 1, 2, 4 or 8 Notes: 1. Output frequency accuracy will depend solely on input reference frequency accuracy. 2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will give improved duty cycle. 3. The minimum output frequency step size is approximately 0.2% due to the divider range provided. 5 AV9110 Figure 1 - Serial Programming AC Timing Parameter tsu1 tsu2 th1 th2 Minimum time (ns) 10 10 10 10 Frequency Acquisition Time Frequency acquisition (or "lock") time is the time that it takes to change from one frequency to another, and is a function of the difference between the old and new frequencies. The AV9 11 0 can typically lock to within 1% of a new frequency in less than 200 microseconds. This is also true with power-on. Jitter For high performance applications, the AV9110 offers extremely low jitter and excellent power supply rejection. The one sigma jitter distribution is typically less than 125ps. For optimum performance, the device should be decoupled with both a 2.2mF and a 0.1mF capacitor. Refer to Recommended Board Layout diagram on page 8. Power-On Reset Upon power-up the internal latches are preset to provide the following output clock frequencies (14.318 MHz reference assumed): Device AV9110-01 AV9110-02 CLK output 25.175 MHz 25.175 MHz CLK/X output 6.29 MHz 12.59 MHz Output Enable The AV9110 outputs can be disabled with either the OE pin or through serial programming. Setting the OE pin low tristates CLK and CLK/X. Alternatively, setting bits D19 and D20 low in the serial word will tristate the two outputs. Both the OE pin and D19 or D20 must be high to enable an output. These preset default frequencies can be changed with a custom metal mask, as can other attributes. The actual numbers of these output clock frequencies (14.318MHz reference assumed) are: Device AV9110-01 AV9110-02 CLK output 25.255 MHz 25.255 MHz CLK/X output 6.31 MHz 12.63 MHz Frequency Transition Glitches The AV9110 starts changing frequency on the rising edge of the 24th serial clock. If the programming of any output divider is changed, the output clock may glitch before locking to the new frequency in less than 200s with no output glitches (no partial clock cycles). and these are within 0.32%. 6 AV9110 AV9110 Quartz Crystal Selection When an external quartz crystal will be used as a frequency reference for the AV9110, attention needs to be given to crystal selection if accurate reference frequency and output frequency is desired. The AV9110 uses a Pierce oscillator design which operates the quartz crystal in parallel-resonant mode. It requires a quartz crystal cut for parallel-resonant operation to ensure an accurate frequency of oscillation (a less expensive series-reso-nant crystal can be used with the device but it will oscillate approximately 0.1% too fast). The AV9110-01 has internal crystal load capacitors which result in a total crystal load capacitance of approximately 12pF10%.The AV9110-02 does not have internal load capacitors, but contributes about 3pFload capacitance to the crystal. Following is a list of recommended crystal devices for the AV9110. They have been tested by the crystal manufacturer to operate suitably with the AV91xx-series crystal oscillator de-sign, having load capacitance characteristics that are compatible with the AV9110-01. Toyocom Part Number TN4-30374 ........ 14.318 MHz surface mount crystal TN4-30375 ........ 20 MHz surface mount crystal TN4-30376 ........ 14.318 MHz through-hole crystal TN4-30377 ........ 20 MHz through-hole crystal Epson Part Number MA-505 or ......... Surface mount crystal MA-506 CA-301 .............. Through-hole crystal Using AV9110-01 with a crystal Using AV9110-01 with an external clock Using AV9110-02 with a crystal Using AV9110-02 with an external clock Figure 2 - Clock Reference Combinations 7 AV9110 AV9110 Recommended Board Layout This is the recommended layout for the AV9110 to maximize clock performance. Shown are the power and ground connections, the ground plane, and the input/output traces. Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise from coupling to the AV9110. As when compared to using the system ground and power planes, this technique will lessen output clock jitter. The isolated ground plane should be connected to the system ground plane at one point near the 2.2mF decoupling cap. For lowest jitter performance, the isolated ground plane should be kept away from clock output pins and traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between the isolated ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line is optional, but will help reduce EMI. The traces to distribute the output clocks should be over an unbroken system ground or power supply plane. The trace width should be about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help minimize clock jitter and EMI radiation. The traces to distribute power should be as wide as possible. 8 AV9110 AV9110 Typical Duty Cycle VCO Output Divide, R = 1 Duty Cycle will improve if R > 1 % MHz AV9110 Idd CL = pF, R = 1 mA MHz 9 AV9110 14-Pin DIP Package 14-Pin 150 mil SOIC Package Ordering Information AV9110-01CN14, AV9110-02CN14 AV9110-01CS14, AV9110-02CS14 Example: ICS XXXX S-PPP X#W Lead Count Lead Count=1,2 or 3 digits Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type S=SOIC N=DIP (plastic) Device Type (consists of 3 or 4 digit numbers) Prefix ICS=Standard Device 10 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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